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Comment: Remove adc_delay and update clock_mode setting

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Note also that reloading the FPGA while the software is running is likely to trigger a kernel panic on the main processor (interrupted PCIe transactions don't seem to be handled well!), and hot-swapping the AMC is equally likely to do this.

Bringing up Software

Measuring timing skew

Each time a new AMC card is commissioned it may be necessary to measure the timing skew from the ADC to the FPGA, and should also be checked when the FPGA image is changed.  This test can be run without any clocks connected (depending on the selected clocking mode) and needs no data input.

Code Block
languagetext
$ tools/scan_idelay -m 499_682
Warning: clock not locked
00 5554 aaa8 aaa8 5554 True False
01 5554 aaa8 aaa8 5554 True False
02 5554 aaa8 aaa8 5554 True False
03 5554 aaa8 aaa8 5554 True False
04 5554 aaa8 aaa8 5554 True False
05 5553 aaa8 aaa8 5554 False False
06 155c aaa8 e659 5554 False False
07 1554 aaa8 eaa8 5554 False False
08 945e aaa8 7fa7 5554 False False
09 a85a aaa8 6e36 5554 False False
0a aaa8 aaa8 5554 5554 True True
0b aaa8 aaa8 5554 5554 True True
0c aaa8 aaa8 5554 5554 True True
0d aaa8 aaa8 5554 5554 True True
0e aaa8 aaa8 5554 5554 True True
0f aaa8 aaa8 5554 5554 True True
10 aaa8 aaa8 5554 5554 True True
11 aaa8 aaa8 5554 5553 False False
12 aaa8 cc53 5554 15d9 False False
13 aaa8 eaa8 5554 1554 False False
14 aaa8 b03f 5554 94cc False False
15 aaa8 6769 5554 aa97 False False
16 aaa8 5554 5554 aaa8 True False
17 aaa8 5554 5554 aaa8 True False
18 aaa8 5554 5554 aaa8 True False
19 aaa8 5554 5554 aaa8 True False

If no clock is connected, or the input clock frequency does not match the programmed mode, or if Passthrough mode is selected then the Warning: clock not locked message will be generated.  Each line of output represents a delay (from data to clock, in steps of 78ps), and the only lines of interest are those ending True True.  From the example above any timing selection in the range 10 to 16 will be valid; our default is 12.

The -m parameter selects the timing mode, and for frequencies other than the default 499.682 MHz a second -f parameter can be used to set the expected range of delays.  For example (output abbreviated):

Code Block
languagetext
$ tools/scan_idelay -m 352_202 -f 352
Only scanning 32 of 37 steps
00 5554 aaa8 aaa8 5554 True False
...
0a aaa8 aaa8 5554 5554 False False
0b aaa8 aaa8 5554 5554 True True
...
11 aaa8 aaa8 5554 5554 True True
12 aaa8 aaab 5554 4cee False False
13 aaa8 eaa8 5554 1554 True False
...
1f aaa8 5554 5554 aaa8 True False

Note that we only have 32 steps of delay available for a maximum delay of 2.5ns.

Preparing IOC Configuration

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KeyDescription
procserv_port
If the IOC is started using the ./start_ioc script this defines the telnet port that procServ will use.  Otherwise this key is ignored.
device_address
This is of the form pci-0000:nn:00.0 where nn identifies the slot where the appropriate AMC525 card is inserted (though the slot numbers and PCIe numbers don't match).  Inspect /dev/amc525_lmbf/ for currently recognised cards.
adc_idelay
This is the timing skew described in the previous section.
dio_termination
If 50Ω termination is wanted for the three digital I/O trigger inputs then set this to 7to 7, otherwise set to 0 for high impedance termination.
clock_mode

This determines how the PLL is initialised.  The following timing modes are supported:

Mode NameDescription
499_682
PLL is locked to 499.682 MHz RF input.
352_202

PLL is locked to 352.202 MHz RF input.

352_372
PLL is locked to 352.372 MHz RF input.
Passthrough
RF clock is passed through without locking and regeneration.

Alternatively this key can be set to sequence of six numbers defining the PLL configuration, for example the following is equivalent to 499_682:

Code Block
languagetext
13 0 5 2 381 61

See the documentation for PLL_ratios in python/lmbf/driver/setup_pll.py for more detail.

epics_name
This determines the top level device name and generally should match $ioc_name determined above.
axis0_name
Name of channel 0.  Typically X for transverse mode, I for longitudinal mode.
axis1_name
Name of channel 1.  Typically Y for transverse mode, Q for longitudinal mode.
lmbf_mode
Set to 0 if operating in transverse mode, set to 1 if longitudinal mode.  This will determine how the FPGA is configured and some details of the behaviour of the IOC.
bunches_per_turn
Set to the number of RF buckets per machine revolution.  Must be no more than 1024 (with the current FPGA build), and there may be problems with particularly small values.
revolution_frequency
Set to machine revolution frequency in Hz.  Only used for time estimates in display.
lmbf_fir_offset
Adjustment of FIR coupling between I and Q axes in LMBF mode.
mms_poll_interval
Used to control polling frequency for MMS readout.  If MMS overrun is reported this number needs to be reduced, but check CPU usage with top.  Reading MMS data is time consuming.
persistence_file
This should be an absolute path to a writeable location where the IOC can save the persistent state of all of its PVs.  It is wise to keep this file backed up and archived as the configuration of MBF can be quite complex and potentially difficult to recreate.
persistence_interval
This determines the interval (in seconds) between checks for writing the persistent state.  Too small a value will generate a lot of writes, too large a value can result in lost configuration state if the IOC is forcibly restarted.
pv_log_array_length
Determines how many points of changed waveforms are logged.
memory_readout_length
Determines the length of the memory readout waveform PV.
detector_length
Determines the length of the detector readout waveform PV.
data_port
Determines socket number for fast data readout.

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