...
Copy the file in /upgrade (using scp) and upgrade the system (you have to use the /upgrade folder as shown below):
| Code Block |
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[root@vtipmi upgrade]# cp DA135-PCIE-x8-1.2.0 /upgrade/
[root@vtipmi upgrade]# cd /upgrade/
[root@vtipmi upgrade]# tar xvzf DA135-PCIE-x8-1.2.0.tgz
DA135-PCIE-x8-1.2.0
DA135-PCIE-x8-1.2.0/vtpcie_ekey.conf
DA135-PCIE-x8-1.2.0/da.conf
DA135-PCIE-x8-1.2.0/upgrade
DA135-PCIE-x8-1.2.0/system.ini
DA135-PCIE-x8-1.2.0/version
DA135-PCIE-x8-1.2.0/plx.eeprom
DA135-PCIE-x8-1.2.0/fruDA.xml
DA135-PCIE-x8-1.2.0/fruGenMCMC
DA135-PCIE-x8-1.2.0/eeprom.pex
[root@vtipmi upgrade]# cd DA135-PCIE-x8-1.2.0
[root@vtipmi DA135-PCIE-x8-1.2.0]# ./upgrade
Backing up /etc/da.conf to /etc/da.conf.bak
Backing up /etc/vtpcie_ekey.conf to /etc/vtpcie_ekey.conf.bak
Creating Daughter Card FRU inventory
warning, no module power information found.
warning, no zone3 compatibility information found.
Updating EEPROM at address 0x50. Please wait ... (try 1)
Verified data in EEPROM 0x50
Erasing the EEPROM...
Resetting the swtich...Done
Writing to EEPROM: Done
Successfully configured daughter card. Please power cycle
for the changes to take affect.
[root@vtipmi DA135-PCIE-x8-1.2.0]# vtipmi start |
...
After power cycling the PCIe link can be x16 at maximum. If you log on the UTC002, you will see:
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[root@vtipmi DA135-PCIE-x8-1.2.0]# pcie
Virtual Link Max Link Link
Device Physical Switch Status Width Width Speed Type
--------------------------------------------------------------------------
1 8 0 Enabled No Link x16 2.5 GT/s Endpoint
2 2 0 Enabled No Link x16 2.5 GT/s Endpoint
3 0 0 Enabled No Link x16 2.5 GT/s Endpoint
4 6 0 Enabled No Link x16 2.5 GT/s Endpoint
5 4 0 Enabled No Link x16 2.5 GT/s Endpoint
6 14 0 Enabled No Link x16 2.5 GT/s Endpoint
7 9 0 Enabled No Link x16 2.5 GT/s Endpoint
8 3 0 Enabled No Link x16 2.5 GT/s Endpoint
9 1 0 Enabled No Link x16 2.5 GT/s Endpoint
10 7 0 Enabled No Link x16 2.5 GT/s Endpoint
11 5 0 Enabled No Link x16 2.5 GT/s Endpoint
12 15 0 Enabled No Link x16 2.5 GT/s Endpoint
13 12 0 Enabled No Link x16 2.5 GT/s Endpoint |
and back on the main system, you can check that PCIe link is taking into account by the system:
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l-utca:~ # lspci
00:00.0 Host bridge: Intel Corporation 2nd Generation Core Processor Family DRAM Controller (rev 09)
00:01.0 PCI bridge: Intel Corporation Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port (rev 09)
00:01.1 PCI bridge: Intel Corporation Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port (rev 09)
00:1d.0 USB controller: Intel Corporation DH89xxCC USB2 Enhanced Host Controller #1 (rev 08)
00:1f.0 ISA bridge: Intel Corporation DH89xxCC LPC Controller (rev 08)
00:1f.2 SATA controller: Intel Corporation DH89xxCC 4 Port SATA AHCI Controller (rev 08)
00:1f.3 SMBus: Intel Corporation DH89xxCC SMBus Controller (rev 08)
00:1f.6 Signal processing controller: Intel Corporation DH89xxCC Thermal Subsystem (rev 08)
00:1f.7 System peripheral: Intel Corporation DH89xxCC Watchdog Timer (rev 08)
01:00.0 Co-processor: Intel Corporation DH89XXCC Series QAT (rev 21)
01:00.1 Ethernet controller: Intel Corporation DH8900CC Series Gigabit Backplane Network Connection (rev 21)
01:00.2 Ethernet controller: Intel Corporation DH8900CC Series Gigabit Backplane Network Connection (rev 21)
01:00.3 Ethernet controller: Intel Corporation DH8900CC Series Gigabit Network Connection (rev 21)
01:00.4 Ethernet controller: Intel Corporation DH8900CC Series Gigabit Network Connection (rev 21)
02:00.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:00.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:01.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:04.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:05.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:08.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:09.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:0c.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab) |