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Benoît Roche

Benoît Roche

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You have to power cycle the crate for the changes to be taken into account.

After power cycling (maybe one more reboot of the AMC720 is also require) the PCIe link can be x16 x8 at maximum. If you log on the UTC002, you will see:

Code Block
languagebash
[root@vtipmi DA135-PCIE-x8-1.2.0~]# pcie
                    Virtual           Link     Max    Link       Link
Device   Physical   Switch  Status    Width    Width  Speed      Type
--------------------------------------------------------------------------
1        8          0       EnabledDisabled   No Link  x16x8     2.5 GT/s   EndpointDownstream
2        21          0       Enabled   x8   No   Link x8 x16    28.50 GT/s   EndpointDownstream
3        0          0       EnabledDisabled   No Link  x16x8     2.5 GT/s   EndpointDownstream
4        65          0       EnabledDisabled   No Link  x16x8     2.5 GT/s   EndpointDownstream
5        4          0       EnabledDisabled   No Link  x8 x16    2.5 GT/s   EndpointDownstream
6        1413         0       Enabled   x8  No    Link x8 x16    25.50 GT/s   EndpointUpstream
713        9 12         0       Enabled   No Link  x16    2.5 GT/s   Endpoint
8        3          0       Enabled   No Link  x16    2.5 GT/s   Endpoint
9        1          0       Enabled   No Link  x16    2.5 GT/s   Endpoint
10       7          0       Enabled   No Link  x16    2.5 GT/s   Endpoint
11       5          0       Enabled   No Link  x16    2.5 GT/s   Endpoint
12       15         0       Enabled   No Link  x16    2.5 GT/s   Endpoint
13       12         0       Enabled Disabled  No Link  x8 x16    2.5 GT/s   Endpoint

...

Downstream

This capture was taken with FPGA image loaded, otherwise the output of pcie will be slightly different. The important point here is to have a max width of x8.

Back on the AMC720, you can check that PCIe link is taking into account by the system:

Code Block
languagebash
l-utca:~ # lspci
00:00.0 Host bridge: Intel Corporation 2nd Generation Core Processor Family DRAM Controller (rev 09)
00:01.0 PCI bridge: Intel Corporation Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port (rev 09)
00:01.1 PCI bridge: Intel Corporation Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port (rev 09)
00:1d.0 USB controller: Intel Corporation DH89xxCC USB2 Enhanced Host Controller #1 (rev 08)
00:1f.0 ISA bridge: Intel Corporation DH89xxCC LPC Controller (rev 08)
00:1f.2 SATA controller: Intel Corporation DH89xxCC 4 Port SATA AHCI Controller (rev 08)
00:1f.3 SMBus: Intel Corporation DH89xxCC SMBus Controller (rev 08)
00:1f.6 Signal processing controller: Intel Corporation DH89xxCC Thermal Subsystem (rev 08)
00:1f.7 System peripheral: Intel Corporation DH89xxCC Watchdog Timer (rev 08)
01:00.0 Co-processor: Intel Corporation DH89XXCC Series QAT (rev 21)
01:00.1 Ethernet controller: Intel Corporation DH8900CC Series Gigabit Backplane Network Connection (rev 21)
01:00.2 Ethernet controller: Intel Corporation DH8900CC Series Gigabit Backplane Network Connection (rev 21)
01:00.3 Ethernet controller: Intel Corporation DH8900CC Series Gigabit Network Connection (rev 21)
01:00.4 Ethernet controller: Intel Corporation DH8900CC Series Gigabit Network Connection (rev 21)
02:00.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:00.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:01.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:04.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:05.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:08.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:09.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)
03:0c.0 PCI bridge: PLX Technology, Inc. Device 8764 (rev ab)

The 8 last lines shows that the PCI bus is recognize by the system.