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Guide to MBF Signal Processing

Guide to MBF Signal Processing

Jun 19, 2020

This page presents an introduction to some of the detailed signal processing stages in the Multi-Bunch Feedback processor.

Data Acquisition

The figure below shows the main processing block and how the data capture choices can be routed.


Five data capture destinations are show here:

  • ADC min/max/sum.  This can show data from before or after the ADC input compensation filter, or from ADC data processed by the fill pattern rejection filter.
  • DAC min/max/sum.  This can DAC data from before or after the DAC output pre-emphasis filter, or from scaled feedback FIR data before being selected for output.
  • DRAM.  This can capture a combination of two out of three inputs (ADC/FIR/DAC), where the ADC and DAC inputs can themselves be selected from the inputs described above.
  • Sequencer and PLL detectors.  These can capture compensated ADC data, fill pattern rejected data, or unscaled feedback FIR data.

Output Multiplexer

The figure below sketches the gathering of the five possible output sources into the DAC output.

Each output source is scaled in two stages: there is a fixed scale (and output enable, not shown here), which applies equally to all bunches, together with a separate scaling factor for each bunch together with a final output enable flag.  For the four NCOs the "fixed" output scale is a number in the range 0 to 1, for the feedback FIR signal the scaling is a number in the range 27 to 2-7 (+42dB to -42dB).

For all five sources the bunch by bunch scaling is a number in the range -8 to +8 (so feedback and NCO drive can be reversed for selected bunches if requred) with a resolution of 2-14 (so +18dB to around -80dB).  Note that if the overall gain for an NCO output is more than 0dB the output will inevitably overflow.

Overflow Detection

This figure shows the processing stages together with the overflow detection events at each stage.

PVDescription
:ADC:INP_OVFThis overflow event is signalled if the magnitude of the raw ADC input is greater than the configured threshold.  The ADC data is otherwise unaffected, so this test only serves as a signal that the ADC input level from the front end may need to be reduced.
:ADC:FIR_OVFIf the ADC input compensation filter overflows this event will be signalled and the output will be clipped.  If this occurs then the overall gain of the compensation filter should be reduced to 1 or less.
:FIR:OVFThis overflow occurs if the feedback filter has too much gain: a gain of more than 8 may trigger overflow.  Note that the output will NOT be clipped, and so undesirable noise may be introduced into the output.  It is well to avoid this situation by ensuring the FIR gain is not too high.
:DAC:BUN_OVFThis overflow event can occur if the FIR output gain is set too high: there is limited dynamic range at this stage, so if this event is being seen without :DAC:MMS_OVF or :DAC:MUX_OVF also triggering then it may be desirable to increase the FIR bunch by bunch gain and reduce the "fixed" gain accordingly.  The output is clipped.
:DAC:MMS_OVFThis overflow event samples the FIR data as passed on to the DAC MMS and DRAM stages.  If this is seen it is likely that the :DAC:MUX_OVF event will also be seen.
:DAC:MUX_OVFIf the sum of all scaled FIR and NCO sources overflows the output level then this event is signalled and the output is clipped.
:DAC:FIR_OVFIf the DAC pre-emphasis filter overflows this event will be signalled and the output will be clipped.  Ensure that the overall gain of this filter is 1 or less.